1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, in particular, relates to those comprising a fuse element.
This application is based on Patent Application No. Hei 9-203608 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
A conventional redundancy circuit is known in which, regarding a RAM or the like, a redundant or extra cell is previously formed so as to improve a yield. In such a circuit, if a failure is found in a regular RAM cell, this substandard cell is separated by disconnecting a relevant fuse and is replaced with the above extra cell.
The disconnection or non-disconnection of the fuse is internally represented using a High/Low state or a high impedance state of a signal. The High/Low state can easily be represented using an internal logic. However, judgment of the high impedance state is difficult in the circuit. Therefore, in the conventional circuit, a fuse element is regarded as a resistor element to which current is applied, and necessity of disconnection of the fuse is judged according to a generated potential difference.
FIG. 5 is a circuit diagram showing an example of the conventional redundancy circuit (refer to FIG. 4 in Japanese Patent Application, First Publication, No. Hei 4-342919). In the figure, between the VDD and GND levels, fuse element 1 and resistor element 2 are inserted in a series connection. To a node in the series connection, the input of inverter element 3 and the drain of NMOS element 4 are connected. In addition, the output of the above inverter element 3 is connected to fuse detective output 5 and the gate of the above NMOS element 4, and the source of the NMOS element 4 is connected to the GND.
Operations of the conventional redundancy circuit having the above structure will be explained below. By designing the resistance (value) of fuse element 1 so that it is sufficiently smaller than that of resistor element 2, a High signal is input into inverter 3 from which a Low signal is output while fuse element 1 is not disconnected. Accordingly, a Low signal is output as fuse detective output 5. With resistance Rf of fuse element 1, resistance R of resistor element 2, source voltage Vdd, and threshold Vt of inverter 3, the resistance ratio (i.e., Rf/R) has the following criterion. EQU Rf/R&lt;&lt;Vt/(Vdd-Vt)
On the other hand, while fuse element 1 is disconnected, a Low signal is input into inverter 3 via resistor element 2; thus, a High signal is output from the inverter 3. Therefore, the High level is input into the gate of NMOS element 4 and the element 4 becomes conductive, and thus the input level of inverter 3 becomes "Low". Accordingly, a High signal is output as fuse detective output 5, which is the output from inverter 3. That is, as fuse detective output 5, the Low level is output while fuse element 1 is not disconnected, and the High level is output while fuse element 1 is disconnected.
FIG. 6 is a circuit diagram showing the second example of the conventional redundancy circuit (refer to FIG. 1 in Japanese Patent Application, First Publication, No. Hei 4-342919) as an improved circuit relating to the above first example. In the figure, fuse element 7 is connected with the VDD terminal, and the drain of NMOS element 8 is connected with the other end of the fuse element 7. The source of the NMOS element 8 is connected to the GND, while the gate of this element is connected to input terminal 6. In addition, the input of inverter element 9 and the drain of NMOS element 10 are connected to the drain of NMOS element 8. The output of the above inverter element 9 is connected with fuse detective output 11 and the gate of the above NMOS element 10, and the source of the NMOS element 10 is connected to the GND.
Operations using the above-explained structure of the second conventional example will be explained with reference to the timing chart of FIG. 7. While fuse element 7 is not disconnected and input terminal 6 has a Low level in the initial phase, NMOS element 8 is not conductive and a High signal is input into inverter 9 via fuse element 7 and a Low signal is output from the inverter. Therefore, the Low signal is output as fuse detective output 11. If the resistance of fuse element 7 is designed to be sufficiently smaller than the resistance between the source and the drain of NMOS element 8 in a conductive state, a High signal is input into inverter 9 while the input terminal 6 has a High level. Therefore, a Low signal is output from the inverter 9 and the Low signal is output as fuse detective output 11.
For example, with resistance Rf of fuse element 7, total resistance R of a series of the resistance of conductive NMOS element 8 and the resistance of another resistor (which is inserted in a series form because it is generally difficult for the NMOS element to obtain a desirable amount of resistance), source voltage Vdd, and threshold Vt of inverter element 9, the resistance ratio (i.e., Rf/R) has the following criterion. EQU Rf/R&lt;&lt;Vt/(Vdd-Vt)
While fuse element 7 is disconnected and input terminal 6 has a Low level in the initial phase, NMOS element 8 is not conductive and the input of inverter element 9 becomes indefinite and then fuse detective output 11 becomes its initial state. On the other hand, while input terminal 6 has a High level, NMOS element 8 is conductive and a Low signal is input into inverter element 9 which then outputs a High signal. In addition, the High signal is input into the gate of NMOS element 10, and this element 10 becomes conductive and the input of inverter 9 becomes "Low". Therefore, as fuse detective output 11, a High signal is output, which is the output of inverter element 9.
Even after input terminal 6 changes from a High level to a Low level and NMOS element 8 becomes non-conductive (i.e., the "off" state), data of the "High" state at input terminal 6 is secured via inverter 9 and NMOS element 10, and a High signal is output as fuse detective output 11. That is, after fuse 7 is disconnected with input terminal 6 being in a High state, regardless of the state of the input terminal, a Low signal is output as fuse detective output 11 while fuse element 7 is not disconnected, and a High signal is output as fuse detective output 11 while fuse element 7 is disconnected.
Next, FIG. 8 is a circuit diagram showing the third example (refer to FIG. 1 in Japanese Patent Application, First Publication, No. Hei 7-14924) as an improved circuit relating to the above examples. In the figure, PMOS element 13 and NMOS element 14 are connected with each other in a complementary form, which thus realizes inverter 23. Fuse element 15 is inserted between the source of NMOS element 14 and the GND. Similarly, PMOS element 18 and NMOS element 17 are complementarily connected, which thus realizes inverter 24. Fuse element 16 is inserted between the source of NMOS element 17 and the VDD. The inputs of inverters 23 and 24 are connected with input terminal 12, and to the output of inverter 23, the input of inverter 19 and the output of inverter 20 are connected. In addition, to the output of inverter 24, the input of inverter 20, the output of inverter 19, and fuse detective output 21 are connected.
Operations using the above-explained structure of the third conventional example will be explained with reference to the timing chart of FIG. 9. While fuse elements 15 and 16 are not disconnected and input terminal 12 has a Low level in the initial phase, inverter 23 outputs a High signal and inverter 24 outputs a Low signal. Therefore, the High signal is input into inverter 19 which then outputs a Low signal, while the above Low signal is input into inverter 20 which then outputs a High signal. The fuse detective output 21 thus becomes "Low". While the above input terminal 12 has a High level, inverter 23 outputs a Low signal and inverter 24 outputs a High signal. The Low signal is input into inverter 19 which then outputs a High signal, while the above High signal is input into inverter 20 which then outputs a Low signal. The fuse detective output 21 thus becomes "High".
While fuse elements 15 and 16 are disconnected and input terminal 12 has a Low level in the initial phase, PMOS elements 13 and 18 are conductive while NMOS elements 14 and 17 are non-conductive. Therefore, a High signal is input into inverter 19 which then outputs a Low signal, while a Low signal is input into inverter 20 which then outputs a High signal. The fuse detective output 21 thus becomes "Low". While the above input terminal 12 has a High level, PMOS elements 13 and 18 are non-conductive while NMOS elements 14 and 17 are conductive.
However, as fuse element 15 is disconnected, the drain of the above NMOS element 14 does not become "Low". Similarly, as fuse element 16 is disconnected, the drain of the above NMOS element 17 does not become "High". Therefore, the input terminal 12 maintains the Low level via inverter elements 19 and 20 and fuse detective output 21 is thus a Low level. That is, in a High state of input terminal 12, fuse detective output 21 becomes "High" while fuse elements 15 and 16 are not disconnected, and fuse detective output 21 becomes "Low" while fuse elements 15 and 16 are disconnected.
In the first conventional example as shown in FIG. 5, with resistance Rf of fuse element 1, resistance R of resistor element 2, and a source voltage Vdd, even though the fuse is not disconnected, stationary current I(=Vdd/(Rf+R)) flows between the VDD-GND terminals through a path such as VDD.fwdarw.fuse element 1.fwdarw.resistor element 2.fwdarw.GND.
In order to solve the above problem, in the above second conventional example, such stationary current is reduced using a signal input from the outside. However, with resistance Rf of fuse element 7, total resistance R of a series of an NMOS element 8 and another resistor, and a source voltage Vdd, while the fuse is not disconnected and a High signal is supplied to input terminal 6, NMOS element 8 is conductive and stationary current I (=Vdd/(Rf+R), similar to that in the first conventional example) flows between the VDD-GND terminals through a path such as VDD.fwdarw.fuse element 7.fwdarw.NMOS element 8.fwdarw.GND.
Also in order to solve the above problem and to reduce the stationary current, the third conventional example has a CMOS structure between the VDD-GND terminals. However, if the input signal changes from "Low" to "High", or from "High" to "Low", during the non-disconnective state of the fuse, a collision between output signals of inverters 23 and 20 and a collision between output signals of inverters 24 and 19 occur for each change and a current according to each collision flows in the circuit.
In order to solve the above-mentioned problem according to the second conventional example, a signal in which the High-state period is reduced as much as possible is necessary in the fourth conventional example. In addition, in order to solve the above-mentioned problem according to the third conventional example, a signal in which level changes are reduced as much as possible is necessary also in the fourth conventional example. If such a signal cannot be supplied from the outside, it is necessary to construct a signal generating circuit inside; thus, a signal operating at the time of applying a power source, such as a one-shot signal, must be used as an input signal. However, in the design of a one-shot signal generating circuit, dispersion in manufacture, voltage fluctuation, and environmental fluctuation must be considered. In addition, there occurs a problem in which such a generating circuit occupies a large area.